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LTC6957HMS-2#PBF
IC CLK BUFFER DVR 1:2 12MSOP
- Fabricante
- Mfr. Parte #LTC6957HMS-2#PBF
- Paquete 12-TSSOP (0.118, 3.00mm Width)
- Hoja de datos
- En stock6116
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Especificaciones
| Supplier | Analog Devices Inc. |
| Package | Tube |
| ProductStatus | Active |
| Type | Fanout Buffer (Distribution) |
| NumberofCircuits | 1 |
| Ratio-Input:Output | 1:2 |
| Differential-Input:Output | Yes/Yes |
| Input | CML, CMOS, LVDS, LVPECL |
| Output | LVDS |
| Frequency-Max | 300 MHz |
| Voltage-Supply | 3.15V ~ 3.45V |
| OperatingTemperature | -40°C ~ 125°C |
| MountingType | Surface Mount |
| Package/Case | 12-TSSOP (0.118, 3.00mm Width) |
Descripción general
Description
Key points
- 2-output variant (LTC6957 family): HMS indicates the HSMSOP-16 package; -2 denotes two outputs.
- Low jitter / low skew clock distribution suitable for FPGA, SERDES, processors, telecom, and precision ADC/DAC timing.
- Typically operates from a standard supply (e.g., 3.3 V) and accepts a reference clock input; outputs can be configured for compatible signaling standards (per datasheet).
- -PBF signifies RoHS-compliant, lead-free packaging.
What to do next
- Check the LTC6957 datasheet for exact electrical specs, input/output formats, drive strength, power-down features, and recommended app circuits.
- Review the pinout and typical use-cases to ensure compatibility with your reference clock and target devices.
Features
- Dual low-jitter clock outputs (differential) with selectable output formats (LVPECL/LVDS/CMOS)
- Programmable frequency synthesis via an internal/N-divider scheme to derive output frequencies from a reference
- Jitter-cleaning PLL with good phase noise performance
- Independent enable/disable and robust holdover options
- Wide single-supply operation (compatible with common rails around 2.5–3.3 V)
- Industrial temperature range (typical -40°C to 125°C)
- Low power consumption for clock distribution applications
- Small RoHS-compliant package (HMS) with lead-free (#PBF) variant
- Serial or simple control interface for configuring dividers/dividers/modes (often SPI-like)
For exact electrical specs, timing details, and package pinout, please refer to the official LTC6957HMS-2#PBF datasheet.
Package
Pinout
- Function: High-performance jitter-cleaning clock generator/PLL with dual outputs; provides two synchronized clock signals derived from a reference, with selectable division/multiplication for clock distribution (used for precise timing in high-speed interfaces).
Manufacturer
Application
- High-speed clock distribution to FPGAs/ASICs/DSPs
- Clocking SERDES interfaces (PCIe, SATA, JESD204B, other high-speed links)
- Telecom and data‑communication equipment and backplanes
- RF/IF systems and ADC/DAC sampling clocks
- Test and measurement instrumentation and other timing-critical systems
Envío
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Referencia de tarifas de envío (DHL/FedEx):
DHL: El costo de envío oscila entre $25-$45 (0.5kg), con un tiempo de entrega estimado de 2-5 días hábiles.
FedEx: El costo de envío oscila entre $25-$40 (0.5kg), con un tiempo de entrega estimado de 3-7 días hábiles.
UPS: El costo de envío oscila entre $25-$45 (0.5kg), con un tiempo de entrega estimado de 3-7 días hábiles.
TNT: El costo de envío oscila entre $25-$65 (0.5kg), con un tiempo de entrega estimado de 3-7 días hábiles.
EMS: El costo de envío oscila entre $30-$50 (0.5kg), con un plazo de entrega estimado de 7-15 días hábiles.
Correo aéreo registrado: El costo de envío es de $2-$4 (0.1kg), con un tiempo de entrega estimado de 5-20 días hábiles.
Pagos
Payment Methods
El plazo de pago es 100% prepagado.
Actualmente, solo aceptamos los siguientes métodos de pago:
1. de PayPal
2. Tarjeta de crédito/débito
3. Transferencia bancaria
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