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ICE40LP1K-QN84
IC FPGA 67 I/O 84QFN
- Fabricante
- Mfr. Parte #ICE40LP1K-QN84
- Paquete QFN-84
- Hoja de datos ICE40LP1K-QN84 DataSheet
- En stock7587
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Especificaciones
| Package | Tray |
| Series | iCE40™ LP |
| ProductStatus | Active |
| NumberofLABs/CLBs | 160 |
| NumberofLogicElements/Cells | 1280 |
| TotalRAMBits | 65536 |
| NumberofI/O | 67 |
| Voltage-Supply | 1.14V ~ 1.26V |
| MountingType | Surface Mount |
| OperatingTemperature | -40°C ~ 100°C (TJ) |
| Package/Case | 84-VFQFN Dual Rows, Exposed Pad |
Descripción general
Description
Its small size (QN84 package) and low thermal dissipation make it ideal for mobile and embedded systems. The ICE40LP1K-QN84 supports Lattice’s innovative design tools, enabling quick prototyping and development. Additionally, it is characterized by a high-speed performance and flexible architecture, allowing designers to implement complex logic functions while maintaining low power consumption.
Overall, the ICE40LP1K-QN84 is a versatile solution for applications in IoT, consumer electronics, automotive, and industrial automation, providing a balance of performance and efficiency.
Features
1. Logic Cells: Approximately 1,440 logic cells, enabling flexible design configurations.
2. I/O Pins: 84 pins with programmable I/O standards, supporting a range of voltage levels.
3. Low Power: Operates with a low static power consumption of around 300 µA, ideal for energy-sensitive applications.
4. Flash-based: Utilizes a non-volatile flash memory for configuration, ensuring instant-on capability and no need for external configuration memory.
5. Performance: Offers up to 1.2 Gbps I/O performance with built-in support for various protocols.
6. DSP Blocks: Includes dedicated DSP blocks for efficient arithmetic processing.
7. Small Footprint: Compact QFN package, suitable for space-constrained designs.
This FPGA is well-suited for applications in IoT, automotive, and consumer electronics, where low power and small size are critical.
Package
Pinout
The pin functions include:
1. I/O Pins: Configurable as input or output for interfacing with other devices.
2. Power Supply Pins: VCC and GND pins for power distribution.
3. Configuration Pins: For programming the FPGA and managing its configuration.
4. Clock Pins: For receiving clock signals to synchronize operations.
5. JTAG Pins: For boundary-scan testing and programming via the JTAG interface.
This device is designed for applications requiring low power consumption and flexibility in design, making it suitable for various embedded systems and portable devices.
Manufacturer
Application
Equivalent
1. Lattice ECP5 series (e.g., LFE5U-25F)
2. Xilinx 7 Series (e.g., XC7A6)
3. Altera MAX 10 series (e.g., 10M02)
However, direct equivalence depends on the specific application requirements like I/O count, speed, and power consumption. Always verify compatibility for your specific use case.
Envío
Métodos de envíoNosotros
ofrecer servicios de envío globales a través de DHL, FedEx, TNT, UPS, o cualquier otro expediente de su elección.
Referencia de tarifas de envío (DHL/FedEx):
DHL: El costo de envío oscila entre $25-$45 (0.5kg), con un tiempo de entrega estimado de 2-5 días hábiles.
FedEx: El costo de envío oscila entre $25-$40 (0.5kg), con un tiempo de entrega estimado de 3-7 días hábiles.
UPS: El costo de envío oscila entre $25-$45 (0.5kg), con un tiempo de entrega estimado de 3-7 días hábiles.
TNT: El costo de envío oscila entre $25-$65 (0.5kg), con un tiempo de entrega estimado de 3-7 días hábiles.
EMS: El costo de envío oscila entre $30-$50 (0.5kg), con un plazo de entrega estimado de 7-15 días hábiles.
Correo aéreo registrado: El costo de envío es de $2-$4 (0.1kg), con un tiempo de entrega estimado de 5-20 días hábiles.
Pagos
Payment Methods
El plazo de pago es 100% prepagado.
Actualmente, solo aceptamos los siguientes métodos de pago:
1. de PayPal
2. Tarjeta de crédito/débito
3. Transferencia bancaria
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