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AD9559BCPZ
IC CLK TRANSLATOR PLL 72-LFCSP
- Fabricante
- Mfr. Parte #AD9559BCPZ
- Paquete 72-VFQFN Exposed Pad, CSP
- Hoja de datos
- En stock6048
100% original & Nuevo
24 horas listos para el envío
Garantía de 365 días
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Especificaciones
| Supplier | Rochester Electronics, LLC,Analog Devices Inc. |
| Package | Bulk,Tray |
| ProductStatus | Active |
| PLL | Yes |
| MainPurpose | Ethernet, SONET/SDH, Stratum |
| Input | LVDS, LVPECL |
| Output | CMOS, HSTL, LVDS |
| NumberofCircuits | 1 |
| Ratio-Input:Output | 4:4 |
| Differential-Input:Output | Yes/Yes |
| Frequency-Max | 1.25GHz |
| Voltage-Supply | 1.71V ~ 3.465V |
| OperatingTemperature | -40°C ~ 85°C |
| MountingType | Surface Mount |
| Package/Case | 72-VFQFN Exposed Pad, CSP |
Descripción general
Description
Features
- Dual PLLs with fractional-N and integer-N synthesis for multiple independent output frequencies
- Up to eight low-skew clock outputs with selectable output types
- LVPECL, LVDS, CML, and CMOS options
- Programmable drive strength and per-output enable/disable
- Flexible reference handling
- Differential or single-ended references
- Programmable dividers and phase alignment for clock alignment
- Per-output programmable skew/delay to optimize timing budgets
- Spread-spectrum clocking and jitter reduction techniques for clean SERDES clocks
- Power-management features
- Power-down/fault detection and robust power-supply supervision
- Holdover capability in some configurations (if reference is lost)
- Protective, reliable operation across operating ranges
- Packaging: 28-pin LFCSP (BCPZ) suitable for space-constrained designs
Typical applications include clock generation/distribution for JESD204, PCIe, SATA, memory interfaces, SERDES-based systems, and other high-performance digital backplanes. For exact electrical specs and supported configurations, refer to the AD9559 datasheet.
Package
Pinout
- Function: High-performance clock generator and distributor (PLL-based) that takes a reference clock and outputs multiple low-jitter, synchronized clock signals for timing-critical systems.
Manufacturer
Application
- Telecom/network equipment (clock distribution/jitter cleaning for SERDES/PHYs)
- Data communications and computing (FPGA/ASIC reference clocks)
- SerDes interfaces (PCIe, SATA, USB, GigE, Fibre Channel)
- RF/microwave systems needing low-jitter reference clocks
- Test and measurement equipment and lab instrumentation
Equivalent
- Analog Devices: AD9523/AD9528/AD9552 (multi-output clock generators/distributors with jitter management)
- Silicon Labs: Si534x family (8-output jitter-cleaning clock generators)
- Texas Instruments: CDCE72010/CDCE913 (multi-output clock conditioning/distribution)
- Renesas/IDT: CDCM clock-distribution products
For an exact cross-reference, compare input range, output format (LVPECL/LVDS/CMOS), number of outputs, jitter, and supply voltage, then use a cross-reference tool or distributor.
Envío
Métodos de envíoNosotros
ofrecer servicios de envío globales a través de DHL, FedEx, TNT, UPS, o cualquier otro expediente de su elección.
Referencia de tarifas de envío (DHL/FedEx):
DHL: El costo de envío oscila entre $25-$45 (0.5kg), con un tiempo de entrega estimado de 2-5 días hábiles.
FedEx: El costo de envío oscila entre $25-$40 (0.5kg), con un tiempo de entrega estimado de 3-7 días hábiles.
UPS: El costo de envío oscila entre $25-$45 (0.5kg), con un tiempo de entrega estimado de 3-7 días hábiles.
TNT: El costo de envío oscila entre $25-$65 (0.5kg), con un tiempo de entrega estimado de 3-7 días hábiles.
EMS: El costo de envío oscila entre $30-$50 (0.5kg), con un plazo de entrega estimado de 7-15 días hábiles.
Correo aéreo registrado: El costo de envío es de $2-$4 (0.1kg), con un tiempo de entrega estimado de 5-20 días hábiles.
Pagos
Payment Methods
El plazo de pago es 100% prepagado.
Actualmente, solo aceptamos los siguientes métodos de pago:
1. de PayPal
2. Tarjeta de crédito/débito
3. Transferencia bancaria
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